1 SP5768 description the SP5768 is a single chip frequency synthesiser designed for tuning systems up to 3.0ghz and is optimized for low phase noise with comparison frequencies up to 4 mhz. the rf programmable divider contains a front end dual modulus 16/17 functioning over the full operating range and allows for coarse tuning in the upconverter application and fine tuning in the downconverter. comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. a buffered reference frequency output is also available to drive a second SP5768. the device also contains 4 switching ports. features complete 3.0ghz single chip system optimised for low phase noise, with comparison frequencies up to 4 mhz no rf prescaler selectable reference division ratio reference frequency output selectable charge pump current integrated loop amplifier four switching ports low power replacement for sp5658 and 5668 downwards software compatible with sp5658 esd protection, (normal esd handling procedures should be observed) applications tv, vcr and cable tuning systems communications systems figure 1 - SP5768 block diagram port p1/oc rf input 16/17 13 bit count 4 bit count reference divider ref crystal charge pump drive 17 bit latch 6 bit latch data clock enable data interface 5 bit latch & port/ test mode interface port p0/op port p2 port p3 crystal cap SP5768 3.0ghz low phase noise frequency synthesiser ds5077 issue 1.4 july 2001 ordering information SP5768/kg/mp1s (tubes) SP5768/kg/mp1t (tape and reel) SP5768/kg/qp1s (tubes) SP5768/kg/qp1t (tape and reel)
2 SP5768 figure 2 - pin connections diagram mp16 qp16 charge pump crystal cap crystal enable data clock port p1/oc port p2 drive v ee rf input rf input v cc ref port p0/op port p3 16 spot ref. electrical characteristics these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. t amb = -40 c to 80 c, v cc = +4 5v to +5 5v characteristic pin value units conditions min typ max supply current 12 18 25 ma rf input frequency range 13,14 100 3000 mhz rf input voltage 13,14 100 300 mv rms 100 - 200mhz 13, 14 30 300 mvrms see figure 6 rf input impedance 13,14 see figure 3 data, clock & enable 5,6,4 input high voltage 3 vcc v input low voltage 0 0.7 v input current -10 10 a all input conditions hysterysis 0.8 v clock rate 6 500 khz bus timing - 5,6,4 data set up 300 ns data hold 600 ns enable set up 300 ns enable hold 600 ns clock to enable 300 ns
3 SP5768 electrical characteristics (continued) these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. tamb = -40 c to 80 c, vcc = +4 5v to +5 5v characteristic pin value units conditions min typ max charge pump output 1 see table 1 current vpin1 = 2v charge pump output 1 3 10 na vpin1=2v, vcc = +5.0v, leakage tamb = 25 c charge pump drive 16 0.5 ma vpin 16=0.7v output current crystal frequency 2,3 2 20 mhz see figure 5 for application external reference input 3 2 20 mhz sinewave coupled through frequency 10f blocking capacitor external reference drive 3 0.2 0.5 v pp sinewave coupled through level 10nf blocking capacitor buffered reference 11 ac coupled, see note 1 frequency output output amplitude 0.35 vpp 2-20mhz output impedance 250 ? comparison frequency 4 mhz equivalent phase noise -148 dbc/hz at 10 khz, ssb, with 2 mhz at phase detector comparison from 4 mhz crystal reference rf division ratio 240 131071 reference division ratio 2 320 see table 2 output ports p0-p3 7,8,9,10 see note 2 sink current 2 ma vport = 0.7v leakage current 10 a vport = vcc 1 reference output disabled by connecting to vcc if not required 2 output ports high impedance on power up, with data, clock and enable at logic 0
4 SP5768 absolute maximum ratings all voltages are referred to vee at 0v characteristic pin min typ max units conditions supply voltage, vcc 12 -0.3 7 v rf input voltage 13,14 2.5 v p-p differential rf input dc offset 13,14 -0.3 v cc +0.3 v port voltage 7,8,9,10 -0.3 v cc +0.3 v charge pump dc offset 1 -0.3 v cc +0.3 v varactor drive dc offset 16 -0.3 v cc +0.3 v crystal dc offset 2,3 -0.3 v cc +0.3 v buffered ref output 11 -0.3 v cc +0.3 v data, clock & enable 5,6,4 -0.3 v cc +0.3 v dc offset storage temperature -55 +125 c junction temperature +150 c mp16 thermal resistance, chip to ambient 80 c/w chip to case 20 c/w power consumption at 138 mw all ports off v cc =5.5v esd protection 2 kv mil-std 883b latest revision method 3015 cat.1. functional description the SP5768 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete pll frequency synthesised source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. the package and pin allocation is shown in figure 1 and the block diagram in figure 2. the SP5768 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. the programming word contains 28 bits, four of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits rd & r0-r2, see table 2, two bits to set charge pump current, bit c0 and c1, see table 1, and the remaining bit to access test modes, bit t0, see table 3. the programming format is shown in figure 4. the clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. this load is also synchronised with the programmable divider so giving smooth fine tuning. the rf signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier is fed to the 17 bit fully programmable counter, which is of mn+a architecture. the m counter is 13 bit and the a counter 4 the output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in table 2. the output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. the charge pump current setting is described in table 1, a buffered crystal reference frequency suitable for driving further synthesisers is available from pin 11. if not required this output can be disabled by connecting to vcc the programmable divider output divided by 2, fpd/2 and comparison frequency, fcomp can be switched to ports p0 and p1 respectively by switching the device into test mode. the test modes are described in table 3.
5 SP5768 figure 3 - rf input impedance table 1 - charge pump current figure 4 - data format s 11 : zo = 50 ? normalised to 50 ? frequency markers at 500mhz, 1ghz, 1.5ghz and 2.4ghz -j1 2 1 3 4 +j0.2 +j0.5 +j1 +j2 +j5 -j5 -j2 -j0.5 -j0.2 0 frequency data p1 p0 t0 c1 c0 r2 r1 r0 rd msb lsb 2 25 2 0 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 2 26 2 27 p2 p3 2^16 to 2^0 : programmable divider ratio control bits r2,r1,r0 : reference divider control bits rd : reference divider mode select p3, p2, p1,p0 : port control bits c1,c0 : charge pump current select t0 : test mode enable data clock enable c1 c0 current (in a) 0 0 230 0 1 1000 1 0 115 1 1 500
6 SP5768 figure 5 - crystal oscillator application table 2 - reference division ratio table 3 - test modes 2 3 SP5768 39pf 18pf rd r2 r1 r0 ratio 00002 00014 00108 001116 010032 010164 0110128 0111256 10003 10015 101010 101120 110040 110180 1110160 1111320 p1 p0 t0 functional description x x 0 normal operation 0 0 1 charge pump sink 0 1 1 charge pump source 1 0 1 charge pump disable 1 1 1 port p1 = fcomp, p0 = fpd/2 x = don't care
7 SP5768 figure 6 - typical input sensitivity 1000 3000 frequency (mhz) 200 operating window 300 100 30 10 vin (mv rms int o 50 ? ) 100 figure 7 - example of double conversion from vhf/uhf frequencies to tv if control micro 2n2 68pf +30v +5v 22k 1k or +12v 4n7 bcw31 1n 1n 10n p1 tuner oscillator output SP5768 13k3 p0 clock data enable optional application utilising on?oard crystal controlled oscillator 1 12 2 3 4 5 6 7 11 10 9 8 13 14 4mhz 18pf 2 3 39pf reference p3 p2 15 16 figure 8 - typical application SP5768 vco vco 10nf 50 - 900mhz 38.9mhz 1650-2700mhz 2 3 10 3 sp5748 sp5748 1.6ghz 1650 -2400mhz 11 SP5768 SP5768
8 SP5768 application notes a generic set of application notes an168 for designing withsynthesisers such as the SP5768 has been written. this covers aspects such as loop filter design and decoupling. this application note is also featured in the media data book, or refer to the zarlink semiconductor internet site http://www.zarlink.com. loop bandwidth the majority of applications for which the SP5768 is intended require a loop filter bandwidth of between 2khz and10khz. typically the vco phase noise will be specified at both 1khz and10khz offset. it is common practice to arrange the loop filter bandwidth such that the 1khz figure lies within the loop bandwidth. thus the phase noise depends on the synthesiser comparator noise floor, rather than the vco. the 10khz offset figure should depend on the vco providing the loop is designed correctly, and is not underdamped. reference source the SP5768 offers optimal lo phase noise performance when operated with a large step size. this is due to the fact that the lo phase noise within the loop bandwidth is: phase comparator lo frequency noise floor + 20 log 10 phase comparator frequency assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall lo to phase comparator division ratio is a minimum. there are two ways of achieving a higher phase comparator sampling frequency: a) reduce the division ratio between the reference source and the phase comparator b) use a higher reference source frequency. approach b) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. ( )
9 SP5768 reference oscillator output ports port v ref 500 500 rf inputs reference output v cc ref 1.2ma v cc bias 25k v cc charge pump drive 200 crystal v cc crystal cap rf inputs loop amplifier disable, enable, data and clock inputs input figure 9 - input/output interface circuits
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at
|
